It's the time of year to remember that the Wireless Waffle list of 100 Halloween Hits is an ideal list of tracks for any spooky party playlist. The list now extends to over 130 songs and includes many chilling classics, as well as some sinister songs you may have never heard of before on topics such as witches, angels, ghosts, nightmares, devils, monsters, freaks, creeps and more.

If you've never noticed that this eerie little trick or treat is hidden away on the web-site, now is the time that you take a look, but be aware, its ghoulish nature may shiver your timbers to their core. So get out your rosary beads, dress up in a torn white blood-curdling bed sheet, smear your face in terrifying tomato ketchup, and hollow out a panicked pumpkin and put a candle in it and go to the local bar and join the others who are similarly attired.

And so here it is, the completed 1 Watt phase locked loop (PLL) FM transmitter. The transmitter part is as exactly as described in part 12, so in this installment of 'How not to design transmitters and receivers' we shall examine the full transmitter including the phase locked loop (PLL).



Here's how it works... Some of the signal from the voltage controlled oscillator (VCO) has been tapped off via a 1 K resistor to reduce the amount that is fed to the pre-scaler. The oscillator provides more than sufficient output to feed both the pre-scaler and the transmitter, so there is no need in this case for any additional buffer between the VCO and the pre-scaler. The pre-scaler (the MB501L) is set to divide by 64 meaning, for example, that with the VCO operating at 100 MHz, the output will be at 1.5625 MHz. A single transistor NPN level buffer has been used between the pre-scalar and the 'divide by N' chip to increase the voltage from the approximately 1.5V peak-to-peak signal at the output of the MB501L to the full supply range needed for the CMOS chip.

Next the reference oscillator. A 4060 IC has been used, with a 6.4 MHz crystal. The division ratio of the 4060 that has been selected is 2¹⁴ (oddly labelled Q13 in the schematic), or 16384, yielding an output from this chip at 390.625 Hz.

In order for the loop to lock, it is therefore necessary to divide the 1.5625 MHz coming from the pre-scaler down to 390.625 Hz. At an operating frequency of 100 MHz, this requires a division ratio of exactly 4000. If we wish the transmitter to operate over the whole of the FM band, for example, then we will require division ratios ranging from 3500 (for 87.5 MHz) to 4320 (for 108 MHz). The binary values for these ratios are shown in the table below.

Digits	212	211	210	29	28	27	26	25	24	23	22	21	20
	4096	2048	1024	512	256	128	64	32	16	8	4	2	1
3500 (87.5)	0	1	1	0	1	1	0	1	0	1	1	0	0
4000 (100.0)	0	1	1	1	1	1	0	1	0	0	0	0	0
4320 (108.0)	1	0	0	0	0	1	1	1	0	0	0	0	0

A couple of things have been highlighted:

• Bits 10 and 11 (1024 and 2048) are either both '1' or both '0'. This holds true across the whole of the frequency range from 87.5 to 108.0 (indeed it holds true from binary 3072 [76.8] MHz to 5119 [127.975 MHz]). These two bits (coloured orange) can therefore be linked together.
• Bits 0 and 1 (1 and 2) are both '0' in both cases. This holds true for any frequency which is a mulitple of 100 kHz. These two bits can therefore be ignored.

The benefits of this are that a 10-way switch can be used to set all 13 bits (i.e. bits 0 to 12) as two are connected together and two are ignored. This can be seen in the circuit diagram where the diodes connected to the counter 'Q10' and 'Q11' outputs are linked together to a single switch. A 4040 IC has been used as the counter. After the MB501L has done all the hard work of dividing down the VHF frequency to one that is just over a MHz, the standard version of this chip is more than sufficient to switch at around 1.5 MHz, and the 74HC (high speed CMOS) version isn't necessary.

A feed from Q11 has been taken from the chip to feed into the phase comparator. The phase comparator used is the good old (literally) 4046. This has two outputs of interest:

• The 'Pulse Phases' (PP) output (pin 1) goes low every time the phase comparator outputs an error voltage, meaning that if the loop is in lock, this pin sits at a positive voltage. Connecting an LED from this pin to ground (through a suitable current limiting resistor) thus acts as a lock detector, the LED growing increasingly bright as the PLL is locked. It can be informative to connect a headphone to this pin (via, say, a 4.7K resistor) as you will get an auditory indication of the two input frequencies and how far apart they are.
• The 'Phase Comparator 2' (PC2) output (pin 13) is used as the output of the phase detector itself. This pin will output a logic 'high' pulse if the divided down phase/frequency of the loop is lower than the reference frequency and a logic 'low' if the phase/frequency is too high. Suitably filtered, this output can be fed to the varicap diodes in the loop to correct the loop frequency.

The output of the PC2 pin goes through a 'lead-lag' type low pass filter. The purpose of this filter is to remove any 390Hz content from the phase detector as this would otherwise be heard modulating the VCO, and to act to slow down the control voltage so that the loop does not respond to low frequency modulation. As designed, the loop filter is set for a frequency of around 1 Hz which should be plenty slow enough. A loop filter this slow would typically be useless in most PLL applications as it means the loop takes several seconds to lock, however as FM transmitters don't change frequency very often (if at all), and given the advantages brought about by ignoring any deep bass modulating the transmitter, in this application it is ideal.

No circuit for producing the necessary regulated 10 Volt (or 5 Volt) supply has been shown: If you can't work out how to produce such a voltage, there's little chance of you being able to build the transmitter correctly.

You have probably noted that this series is entitled 'How not to design transmitters and receivers', and so far all that has been covered are transmitters. So, in ensuing instalments, the building blocks required to build a receiver together with the many pitfalls which can trap you when doing this will be discussed.

The previous parts of the "How not to design transmitters and receivers" series have described all the design decisions and blocks which need to go together to produce a 1 Watt wideband FM transmitter. It is now time to start putting those blocks together into a full-blown design.

First up is the 1 Watt transmitter chain itself, composed of:

• a voltage controlled oscillator (VCO) as described in part 1
• a buffer amplifier which is not totally dissimilar to those described in part 6,
• a matching circuit between the buffer and the power amplifier, as described in part 3,
• a 1 Watt power amplifier, based on a device identified in part 2, and
• a low-pass filter, as described in part 9.

The circuit diagram below shows these elements put together (click on the image for a larger version).



The VCO should be set to oscillate at half the wanted output frequency. The '2f' component of this is then passed to the buffer which is formed of the 2SC3356. The 22pF capacitor between them is not critical. Other transistors which can produce around 100mW of power would be equally suitable in the buffering role, such as the MPSH10. The output of the buffer is fed into the power amplifier and then through a low pass filter. The output transistor (the MRF555) can also be replaced by different devices, however the matching network between the buffer and the output stage may require alteration.

No phase locked loop (PLL) circuitry is yet shown, this will follow in an ensuing post. As illustrated, the design is called a 'free running' oscillator meaning that its output frequency is set only by the control voltage applied to its input, the value of the centre-tapped inductor in the circuit, and the variable capacitor which sits across it. This design is relatively stable and after settling down has an accuracy of better than a few kHz at an output frequency of 100 MHz, as long as the control voltage remains constant and the temperature isn't allowed to drift too much.

In operation, the BF451's should draw around 10 mA each, the 2SC3356 (or equivalent) should draw around 15 mA and the output device in the region of 150mA. If constructing a prototype based on this schematic, ensure that good radio frequency (RF) construction principles are adhered to, in particular:

• The leads of all components should be kept as short as possible, and certainly not be allowed to exceed 1 cm in length. This is because a simple piece of wire will act as an inductor at RF and introduce unwanted reactance to the circuit.
• Ideally, the circuit should be built over a solid ground-plane which acts as the ground connection. A piece of un-etched copper-clad printed circuit board (PCB) material will do the job handsomely.

Note that the 10V supply which feeds both the VCO and the buffer should be regulated using, for example, one of the designs discussed in part 4.

In an earlier 'How not to design transmitters and receivers' it was blithely stated that the reference oscillator part of a phase locked loop (PLL) was a relatively trivial undertaking. And... it is. All that needs to be decided is what the reference frequency is going to be.

Throughout these series of articles, a reference frequency of 100 kHz has been used in order to illustrate how a variable frequency PLL operates. However, this would require that the output frequency is fed directly into the 'divide by N' block, and as has also been discussed, these devices do not usually operate at frequencies as high as 100 MHz, indeed many of the purpose-designed divide by N chips (such as the TC9122P) will only cope with input frequencies as high as 10 to 15 MHz. In addition, as was discussed in part 5, the lower the reference frequency, the less the PLL will see modulation as a frequency error and try and correct it. A reference frequency of 100 kHz is therefore both difficult to work with (due to the divide by N frequency limitations) and too high (due to the PLL trying to correct modulation).

How high should the reference frequency be then? In many PLL designs for FM transmitters, this is often set to be in the order of 10 kHz, though some designs are nearer 1 kHz. For the Wireless Waffle lockdown project, it was decided to use an even lower frequency, so that the low frequency audio response of the PLL could be as flat as possible.

To define the exact frequency, the amount by which the prescaler initially divides down the output frequency must be factored in. The previously discussed MB501L can be set to divide by 64 or 128. If either of these were immediately followed by a divide by N, which could count in steps of 1 and with each step being 100 kHz, then the maximum reference frequency would be either 1.5625 kHz (100 kHz / 64) or 781.25 Hz (100 kHz / 128). The reference frequency could be lower than this if, for example, the divide by N used a higher division ratio (for example, counting in steps of 2). To allow for 25 kHz steps, which are used in some other audio applications such as studio-to-transmitter links, a reference frequency of 390.625 Hz was chosen (i.e. 25 kHz / 64). Note that this means that for each 100 kHz step, the divide by N counter has to be incremented by 4, not 1.

The simplest way of generating a reference frequency is to use the tried and tested 4060 IC as shown in the circuit on the right. The 4060 has a built in oscillator (which can be used with quartz crystals such as in this application, or as just with resistors and capacitors) as well as having a binary counter that can easily produce outputs divided by multiples of 2. Even the standard CMOS version of this chip will oscillate at frequencies up to around 8 MHz with a 5 Volt power supply and higher still if the supply voltage is increased.

A crystal with a frequency of 6.4 MHz is easy to source (being a not-uncommon clock frequency) and needs to be divided by 16384 (or 2¹⁴) to produce an output at the required reference at 390.625 Hz. The 4060 has an output which divides by 2¹⁴ on pin 3 so a simple crystal oscillator and divider circuit can be made from this chip alone.

Other CMOS divider chips (such as the 4020, 4024 or 4040) can also be used for dividing down a fixed frequency oscillator but need a stand-alone crystal oscillator to drive them. An example of this arrangement is shown on the left.

Note that the value of resistors around the transistor used as the oscillator are somewhat critical. The exact current flowing through the transistor is not that critical (anywhere in the region of 2 to 5 milliAmps should be OK) however the transistor needs to be biassed such that when it is not oscillating, the collector voltage is close to half the supply voltage. This will mean that when oscillating the output swings equally above and below half the supply voltage, which the CMOS counter, whose input thresholds are similarly symmetrical, will count properly. In the case of the transistor being biassed such that the output when not oscillating sits at say, 3/4 of the supply voltage, it is possible that the peak-to-peak output swing may be reduced and may not be sufficient to drive the CMOS chip. These resistor values will be different depending on the exact transistor used (actually the specific DC current gain, β, or h_FE of the transistor). As with many electronic design problems these days, there's an online tool to help calculate the necessary resistor values..

And so, the end is near, and that final curtain is nearly ready to be opened to a blaze of audience applause. In the next article in this series, everything learnt so far will be soldered together into a single circuit diagram (or schematic, whichever is your preference). And then it will be time to start to think about receivers, and their associated building blocks. Some say that radio frequency (RF) design is a bit of a black art, insofar as there are so many hurdles which can trip you up along the way (if that isn't a badly mixed metaphor). For transmitters, the biggest problems come from unwanted harmonics and crazy spurious oscillations. In receivers there are these things to deal with, but also the need to have a nice clean and distortion path from the input to the output so that the wanted signal can be received, and any unwanted signals can be rejected. Nobody said it was easy.